Petter Gustad <email@example.com> wrote:
| Jouni Matti Juhani Osmala <firstname.lastname@example.org> writes:
| > Petter Gustad <email@example.com> writes:
| > > Ole Myren Rohne <firstname.lastname@example.org> writes:
| > > > Marco Antoniotti <email@example.com> writes:
| > > > > Once you have chosen your Hardware Design Language (VHDL, Verilog...
| > > > That's cheating! He needs to start defining a lisp-based HDL;-)
| > > Well, you could write it in EDIF, which is Lisp :-)
| > Well, I personally like lisp, and dislike VHDL, can EDIF be recommended
| > as a general purpose HDL?
| No (notice the smiley). EDIF is a netlist format. However, you could
| probably write some clever macros and functions in order to produce
| some readable and maintainable HDL descriptions in Common Lisp if you
| had an EDIF simulator (or you could convert the EDIF to verilog prior
| to simulation).
Here's one design/simulation approach, albeit somewhat dated by now:
Rob Warnock, PP-ASEL-IA <firstname.lastname@example.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607